set_attribute library {{
/chalmers/sw/sup/cds/hcmos9gp-9.2/CORE9GPHS_SNPS_AVT_4.1.a/SNPS/bc_1.32V_0C_wc_1.08V_105C/PHS/CORE9GPHS_Nom.lib
/chalmers/sw/sup/cds/hcmos9gp-9.2/CORX9GPHS_SNPS_AVT_7.1.a/SNPS/bc_1.32V_0C_wc_1.08V_105C/PHS/CORX9GPHS_Nom.lib
}}
read_hdl -vhdl ./vhd/custom_types.vhd ./vhd/precalc.vhd ./vhd/RCA.vhd ./vhd/logic_unit.vhd ./vhd/shift_unit.vhd ./vhd/mux16x1.vhd ./vhd/ALU_RCA.vhd
elaborate
define_clock -name main_clk -period 3043 [find / -port Clk]
synthesize -to_mapped -effort medium
report timing > power_constraint_1_timing_report.txt
report gates  > power_constraint_1_gates_report.txt
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_probability 1 /designs/ALU_RCA/ports_in/Reset
set_attribute lp_asserted_toggle_rate 0.0 /designs/ALU_RCA/ports_in/Reset

set_attribute lp_power_analysis_effort medium /

set_attribute hdl_track_filename_row_col true /
report power > power_scenario_1_power_report.txt
report gates -power >> power_scenario_1_power_report.txt
report power Clk >> power_scenario_1_power_report.txt

set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_probability 1 /designs/ALU_RCA/ports_in/Reset
set_attribute lp_asserted_toggle_rate 0.0 /designs/ALU_RCA/ports_in/Reset

set_attribute lp_power_analysis_effort medium /

set_attribute hdl_track_filename_row_col true /
report power > power_scenario_2_power_report.txt
report gates -power >> power_scenario_2_power_report.txt
report power Clk >> power_scenario_2_power_report.txt

read_vcd -static -vcd_module rca_alu ALU_RCA.vcd
report power > power_report_vcd.txt

read_saif -instance rca_alu ALU_RCA.saif
report power > power_report_saif.txt

write_tcf > alu_rca_random.tcf

read_saif -instance rca_alu_real ALU_RCA_real.saif
report power > power_report_saif_real.txt

write_tcf > alu_rca_random_real.tcf


##########################################################################################################
##########################################################################################################
##########################################################################################################
define_clock -name main_clk -period 4043 [find / -port Clk]
synthesize -to_mapped -effort medium
report timing > power_constraint_1_timing_report2.txt
report gates  > power_constraint_1_gates_report2.txt
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_probability 1 /designs/ALU_RCA/ports_in/Reset
set_attribute lp_asserted_toggle_rate 0.0 /designs/ALU_RCA/ports_in/Reset

set_attribute lp_power_analysis_effort medium /

set_attribute hdl_track_filename_row_col true /
report power > power_scenario_1_power_report2.txt
report gates -power >> power_scenario_1_power_report2.txt
report power Clk >> power_scenario_1_power_report2.txt

set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_probability 1 /designs/ALU_RCA/ports_in/Reset
set_attribute lp_asserted_toggle_rate 0.0 /designs/ALU_RCA/ports_in/Reset

set_attribute lp_power_analysis_effort medium /

set_attribute hdl_track_filename_row_col true /
report power > power_scenario_2_power_report2.txt
report gates -power >> power_scenario_2_power_report2.txt
report power Clk >> power_scenario_2_power_report2.txt

read_vcd -static -vcd_module rca_alu ALU_RCA.vcd
report power > power_report_vcd2.txt

read_saif -instance rca_alu ALU_RCA.saif
report power > power_report_saif2.txt

write_tcf > alu_rca_random2.tcf

read_saif -instance rca_alu_real ALU_RCA_real.saif
report power > power_report_saif_real2.txt

write_tcf > alu_rca_random_real2.tcf


##########################################################################################################
##########################################################################################################
##########################################################################################################
define_clock -name main_clk -period 5043 [find / -port Clk]
synthesize -to_mapped -effort medium
report timing > power_constraint_1_timing_report3.txt
report gates  > power_constraint_1_gates_report3.txt
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_probability 1 /designs/ALU_RCA/ports_in/Reset
set_attribute lp_asserted_toggle_rate 0.0 /designs/ALU_RCA/ports_in/Reset

set_attribute lp_power_analysis_effort medium /

set_attribute hdl_track_filename_row_col true /
report power > power_scenario_1_power_report3.txt
report gates -power >> power_scenario_1_power_report3.txt
report power Clk >> power_scenario_1_power_report3.txt

set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_probability 1 /designs/ALU_RCA/ports_in/Reset
set_attribute lp_asserted_toggle_rate 0.0 /designs/ALU_RCA/ports_in/Reset

set_attribute lp_power_analysis_effort medium /

set_attribute hdl_track_filename_row_col true /
report power > power_scenario_2_power_report3.txt
report gates -power >> power_scenario_2_power_report3.txt
report power Clk >> power_scenario_2_power_report3.txt

read_vcd -static -vcd_module rca_alu ALU_RCA.vcd
report power > power_report_vcd3.txt

read_saif -instance rca_alu ALU_RCA.saif
report power > power_report_saif3.txt

write_tcf > alu_rca_random3.tcf

read_saif -instance rca_alu_real ALU_RCA_real.saif
report power > power_report_saif_real3.txt

write_tcf > alu_rca_random_real3.tcf


##########################################################################################################
##########################################################################################################
##########################################################################################################
define_clock -name main_clk -period 6043 [find / -port Clk]
synthesize -to_mapped -effort medium
report timing > power_constraint_1_timing_report4.txt
report gates  > power_constraint_1_gates_report4.txt
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_probability 1 /designs/ALU_RCA/ports_in/Reset
set_attribute lp_asserted_toggle_rate 0.0 /designs/ALU_RCA/ports_in/Reset

set_attribute lp_power_analysis_effort medium /

set_attribute hdl_track_filename_row_col true /
report power > power_scenario_1_power_report4.txt
report gates -power >> power_scenario_1_power_report4.txt
report power Clk >> power_scenario_1_power_report4.txt

set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_probability 1 /designs/ALU_RCA/ports_in/Reset
set_attribute lp_asserted_toggle_rate 0.0 /designs/ALU_RCA/ports_in/Reset

set_attribute lp_power_analysis_effort medium /

set_attribute hdl_track_filename_row_col true /
report power > power_scenario_2_power_report4.txt
report gates -power >> power_scenario_2_power_report4.txt
report power Clk >> power_scenario_2_power_report4.txt

read_vcd -static -vcd_module rca_alu ALU_RCA.vcd
report power > power_report_vcd4.txt

read_saif -instance rca_alu ALU_RCA.saif
report power > power_report_saif4.txt

write_tcf > alu_rca_random4.tcf

read_saif -instance rca_alu_real ALU_RCA_real.saif
report power > power_report_saif_real4.txt

write_tcf > alu_rca_random_real4.tcf

##########################################################################################################
##########################################################################################################
##########################################################################################################
define_clock -name main_clk -period 7043 [find / -port Clk]
synthesize -to_mapped -effort medium
report timing > power_constraint_1_timing_report5.txt
report gates  > power_constraint_1_gates_report5.txt
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_probability 1 /designs/ALU_RCA/ports_in/Reset
set_attribute lp_asserted_toggle_rate 0.0 /designs/ALU_RCA/ports_in/Reset

set_attribute lp_power_analysis_effort medium /

set_attribute hdl_track_filename_row_col true /
report power > power_scenario_1_power_report5.txt
report gates -power >> power_scenario_1_power_report5.txt
report power Clk >> power_scenario_1_power_report5.txt

set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_probability 1 /designs/ALU_RCA/ports_in/Reset
set_attribute lp_asserted_toggle_rate 0.0 /designs/ALU_RCA/ports_in/Reset

set_attribute lp_power_analysis_effort medium /

set_attribute hdl_track_filename_row_col true /
report power > power_scenario_2_power_report5.txt
report gates -power >> power_scenario_2_power_report5.txt
report power Clk >> power_scenario_2_power_report5.txt

read_vcd -static -vcd_module rca_alu ALU_RCA.vcd
report power > power_report_vcd5.txt

read_saif -instance rca_alu ALU_RCA.saif
report power > power_report_saif5.txt

write_tcf > alu_rca_random5.tcf

read_saif -instance rca_alu_real ALU_RCA_real.saif
report power > power_report_saif_real5.txt

write_tcf > alu_rca_random_real5.tcf
##########################################################################################################
##########################################################################################################
##########################################################################################################
define_clock -name main_clk -period 8043 [find / -port Clk]
synthesize -to_mapped -effort medium
report timing > power_constraint_1_timing_report6.txt
report gates  > power_constraint_1_gates_report6.txt
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_toggle_rate 0.02 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_probability 1 /designs/ALU_RCA/ports_in/Reset
set_attribute lp_asserted_toggle_rate 0.0 /designs/ALU_RCA/ports_in/Reset

set_attribute lp_power_analysis_effort medium /

set_attribute hdl_track_filename_row_col true /
report power > power_scenario_1_power_report6.txt
report gates -power >> power_scenario_1_power_report6.txt
report power Clk >> power_scenario_1_power_report6.txt

set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/A*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/B*
set_attribute lp_asserted_probability 0.5 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_toggle_rate 0.1 /designs/ALU_RCA/ports_in/Op*
set_attribute lp_asserted_probability 1 /designs/ALU_RCA/ports_in/Reset
set_attribute lp_asserted_toggle_rate 0.0 /designs/ALU_RCA/ports_in/Reset

set_attribute lp_power_analysis_effort medium /

set_attribute hdl_track_filename_row_col true /
report power > power_scenario_2_power_report6.txt
report gates -power >> power_scenario_2_power_report6.txt
report power Clk >> power_scenario_2_power_report6.txt

read_vcd -static -vcd_module rca_alu ALU_RCA.vcd
report power > power_report_vcd6.txt

read_saif -instance rca_alu ALU_RCA.saif
report power > power_report_saif6.txt

write_tcf > alu_rca_random6.tcf

read_saif -instance rca_alu_real ALU_RCA_real.saif
report power > power_report_saif_real6.txt

write_tcf > alu_rca_random_real6.tcf

##########################################################################################################
##########################################################################################################
##########################################################################################################

# define_clock -name main_clk -period 4043 [find / -port Clk]
# synthesize -to_mapped -effort medium
# report timing > power_constraint_4043_timing_report_and_gates_report.txt
# report gates  >> power_constraint_4043_timing_report_and_gates_report.txt
# read_vcd -static -vcd_module rca_alu ALU_RCA.vcd
# report power > power_report_vcd_4043.txt
# read_saif -instance rca_alu ALU_RCA.saif
# report power > power_report_saif_4043.txt

# define_clock -name main_clk -period 5043 [find / -port Clk]
# synthesize -to_mapped -effort medium
# report timing > power_constraint_5043_timing_report_and_gates_report.txt
# report gates  >> power_constraint_5043_timing_report_and_gates_report.txt
# read_vcd -static -vcd_module rca_alu ALU_RCA.vcd
# report power > power_report_vcd_5043.txt
# read_saif -instance rca_alu ALU_RCA.saif
# report power > power_report_saif_5043.txt

# define_clock -name main_clk -period 6043 [find / -port Clk]
# synthesize -to_mapped -effort medium
# report timing > power_constraint_6043_timing_report_and_gates_report.txt
# report gates  >> power_constraint_6043_timing_report_and_gates_report.txt
# read_vcd -static -vcd_module rca_alu ALU_RCA.vcd
# report power > power_report_vcd_6043.txt
# read_saif -instance rca_alu ALU_RCA.saif
# report power > power_report_saif_6043.txt

# define_clock -name main_clk -period 7043 [find / -port Clk]
# synthesize -to_mapped -effort medium
# report timing > power_constraint_7043_timing_report_and_gates_report.txt
# report gates  >> power_constraint_7043_timing_report_and_gates_report.txt
# read_vcd -static -vcd_module rca_alu ALU_RCA.vcd
# report power > power_report_vcd_7043.txt
# read_saif -instance rca_alu ALU_RCA.saif
# report power > power_report_saif_7043.txt

# define_clock -name main_clk -period 8043 [find / -port Clk]
# synthesize -to_mapped -effort medium
# report timing > power_constraint_8043_timing_report_and_gates_report.txt
# report gates  >> power_constraint_8043_timing_report_and_gates_report.txt
# read_vcd -static -vcd_module rca_alu ALU_RCA.vcd
# report power > power_report_vcd_8043.txt
# read_saif -instance rca_alu ALU_RCA.saif
# report power > power_report_saif_8043.txt